Speaker
Taehyun Tak
(KSTAR Control Research Team)
Description
The ITER Central Interlock System (CIS) architecture is composed of four categories of hardware: fast architecture, slow PLC based architecture, hardwired architecture and servers.
The CIS fast architecture receives interlock events from various local plant systems of ITER and communicates the corresponding actions to any other local plant systems in order to avoid or mitigate the damage to the machine. Such functions require a reaction time that could range from 1 to 10 ms, which is faster than what the PLC are capable. The CIS fast architecture consists of a module named Plasma Protection Module (PPM), mainly in charge of interlock functions related to the plasma.
As well as satisfying time performance requirements, the PPM complies with CIS reliability, availability and integrity requirements (probability of failure per hour below 10-7-7 and failsafe solution).
In this paper, we explain the engineering design of our approach under a technical perspective. A COTS FPGA in a redundant configuration solution, which uses serial communication with the local plant systems, is considered.
Co-authors
Giil Kwon
(KSTAR Control Research Team, National Fusion Research Institute, Daejeon, South Korea)
Gisik Lee
(Mobiis, Seoul, South Korea)
Jaesic Hong
(KSTAR Control Research Team, National Fusion Research Institute, Daejeon, South Korea)
Jungyul Cho
(Mobiis, Seoul, South Korea)
Pedica Riccardo
(Vitrociset, SPA, Via Tiburtina, 1020 - 00156 Roma, Italy)
Prieto Diaz Ignacio
(Iberdrola Ingeniería y Construcción S.A.U., 28050 Madrid, Spain)
Taegu Lee
(KSTAR Control Research Team, National Fusion Research Institute, Daejeon, South Korea)
Taehyun Tak
(KSTAR Control Research Team, National Fusion Research Institute, Daejeon, South Korea)
Woongryol Lee
(KSTAR Control Research Team, National Fusion Research Institute, Daejeon, South Korea)
